The present invention relates generally to integrated circuit devices and methods of operating same and, more particularly, to integrated circuit memory devices and methods of operating same.
When applying input signals to multiple semiconductor memory devices, the effects of loading may need to be taken into account. A memory module may use a register to apply input signals to multiple semiconductor memory devices. The register may reduce the distortion in the input signals due to the load of the memory devices; however, because memory devices occupy different positions in a chip and/or a circuit board, the memory devices receive the input signals at different times. This is illustrated, for example, in FIG. 1.
FIG. 1 is a circuit diagram of a conventional memory module in which a register applies input signals to a plurality of semiconductor memory devices, and FIG. 2 is a timing diagram showing the operation of the memory module shown in FIG. 1. As shown in FIG. 1, a conventional memory module 100 comprises a plurality of semiconductor memory devices M1, M2, . . . , Mn, a register 120, and a phase-locked loop 130.
The phase-locked loop 130 generates a plurality of output clock signals OCLK1, OCLK2, . . . , OCLKn+1, which are in phase with each other, in synchronization with an input clock signal CLK. The register 120 generates output signals ACOUT in response to input signals ACIN and in synchronization with the output clock signal OCLK1. The register 130 may provide increased driving capability to account for the loading effects of the semiconductor memory devices M1, M2, . . . , Mn. The semiconductor memory devices M1, M2, . . . , Mn respectively receive the output signals ACOUT in synchronization with the output clock signals OCLK2, . . . , OCLKn+1.
Referring now to FIG. 2, transitions in the output signals ACOUT are synchronized with rising edges of the output clock signal OCLK1. Thus, as shown in FIG. 2, input signals ACIN are enabled when driven low, and the time that the input signals ACIN are enabled is different from the time that the output signals ACOUT are enabled. The length of time that the output signals ACOUT are enabled is equal to the period of the output clock signal OCLK1.
As shown in FIG. 2, the output signals ACOUT are delayed for variable lengths of time before they are applied to the plurality of semiconductor memory devices M1, M2, . . . , Mn. For example, semiconductor memory device Mn is closest to the register 120 and semiconductor memory device M1 is farthest from the register 120; therefore, the output signals ACOUT are received by semiconductor device Mn (illustrated by ACOUT_MN) before the output signals ACOUT are received by the semiconductor device M1 (illustrated by ACOUT_M1). Because the output signals ACOUT are generated in response to the input signals ACIN and in synchronization with the output clock signals OCLK1, OCLK2, . . . , OCLKn+1, which all have the same phase, the setup and hold times of the output signals ACOUT applied to the semiconductor memory devices M1, M2, . . . , Mn may not be within desired operating margins for one or more of the semiconductor memory devices M1, M2, . . . , Mn. The phase of the input clock signal CLK and the output clock signals OCLK1, OCLK2, . . . , OCLKn+1 may be pushed and/or pulled by controlling the capacitance of capacitors CAP1 and CAP2 to adjust the setup and hold times; however, the effectiveness of this approach may be limited. The register 120 generates the output signals ACOUT in response to the input signals ACIN and in synchronization with the output clock signal OCLK1. Moreover, the output signals OCLK2, . . . , OCLKn+1 are in phase with the output clock signal OCLK1 and are used by the semiconductor memory devices M1, M2, . . . , Mn to synchronize the reception of the output signals ACOUT. Thus, the plurality of semiconductor memory devices M1, M2, . . . , Mn may not affected by controlling setup and hold times of the first input signals ACIN.
According to embodiments of the present invention, an integrated circuit device comprises a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal. The multiple devices may comprise memory devices.
In other embodiments of the present invention, the delay circuit comprises a memory unit that is configured to store delay information therein and a delay buffer that is coupled to the memory unit and is configured to generate the delayed clock signal at an output terminal thereof in response to the delay information and the clock signal received at an input terminal thereof.
In still other embodiments of the present invention, the delay buffer comprises a plurality of buffers and a plurality of switches that are respectively operable to connect selected ones of the plurality of buffers in series between the input terminal and the output terminal of the delay buffer.
In still other embodiments of the present invention, the delay circuit further comprises a demultiplexer circuit that couples the memory unit to the delay buffer and is configured to generate a plurality of switch control signals. Respective ones of the plurality of switches are responsive to the respective ones of the plurality of switch control signals.
In still other embodiments of the present invention, the delay circuit further comprises a receiver circuit that is configured to store the input data signal and to generate the output data signal in response to the delayed clock signal and the stored input data signal.
In still other embodiments of the present invention, an input terminal is coupled to both the receiver circuit and the memory unit and is configured to receive the input data signal and the delay information therethrough.
In still other embodiments of the present invention, a clock generation circuit is configured to generate the clock signal in response to an input clock signal. The clock generation circuit may be a phase locked loop circuit.
In further embodiments of the present invention, an integrated circuit device comprises a delay circuit that is configured to receive an input data signal in response to a clock signal and is further configured to generate an output data signal by delaying the input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal. The multiple devices may comprise memory devices.
In still further embodiments of the present invention, an integrated circuit device comprises a plurality of delay circuits that are respectively configured to delay a clock signal so as to generate a plurality of output clock signals having differing phases. A storage circuit is configured to generate an output data signal in response to an input data signal and one of the plurality of output clock signals. Multiple devices are configured to respectively receive the output data signal in response to respective other ones of the plurality of output clock signals.
Although embodiments of the present invention have been described above primarily with respect to apparatus embodiments, embodiments of methods of operating integrated circuit devices are also provided.